nv40_reg.h

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#ifndef __NV40_REG_H__
#define __NV40_REG_H__

#define NV40_VTX_FORMAT 0x1740
#define NV40_VTX_FORMAT_TYPE_SHIFT          0
#define NV40_VTX_FORMAT_TYPE_MASK           (0x0F << 0)
#    define NV40_VTX_FORMAT_TYPE_FLOAT      2
#    define NV40_VTX_FORMAT_TYPE_UBYTE      4
#define NV40_VTX_FORMAT_NCOMP_SHIFT         4
#define NV40_VTX_FORMAT_NCOMP_MASK          (0x0F << 4)
#define NV40_VTX_FORMAT_STRIDE_SHIFT        8
#define NV40_VTX_FORMAT_STRIDE_MASK         (UNKNOWN << 8)

/* This is a list of memory addresses pointing to the vertex/colour(etc) data
 *
 * It appears that this is ordered in the same way that the vertex format
 * descriptions are, with unused slots being filled with 0x00000000.
 * 
 * NOTE: For me, the vertex weight has always been specified as the same
 * location as the vertex positions..
 */
#define NV40_VB_POINTER 0x1680

/* It seems that you can only send vertices in groups of 256 at a time.
 * The proprietary driver will send a batch of (vertices % 256) first, and
 * then send the remaining vertices in lots of 256 in a separate command.
 *
 * ie: 516 vertices
 *  52d   0x00000000   0x00043814   {size: 0x1   channel: 0x1   cmd: 0x00001814}
 *  52e   0x00000000   0x03000000
 *  52f   0x00000000   0x40083814   {size: 0x2   channel: 0x1   cmd: 0x40001814}
 *  530   0x00000000   0xff000004
 *  531   0x00000000   0xff000104
 *
 * Also, note that the second 0x1814 command has bit 30 set.. not sure what
 * the significance of that is..
 */
#define NV40_VB_VERTEX_BATCH 0x1814
#define NV40_VB_VERTEX_BATCH_OFFSET_SHIFT   0           /* offset in vertices */
#define NV40_VB_VERTEX_BATCH_OFFSET_MASK    (0xFFFFFF << 0) /* guess */
#define NV40_VB_VERTEX_BATCH_COUNT_SHIFT    24          /* count in vertices  */
#define NV40_VB_VERTEX_BATCH_COUNT_MASK     (0xFF << 24)

#define NV30_TX                                            0x00001A00
#define NV30_TX_UNIT(n)                                    (0x1A00 + (n * 32))
/* DWORD 0 - texture address */
/* DWORD 1 */
#  define NV30_TX_MIPMAP_COUNT_SHIFT                    20
#  define NV30_TX_MIPMAP_COUNT_MASK                     (0xF << 20) /* guess */
#  define NV30_TX_NPOT                                  (1 << 13)    /* also set on RECT, even if POT */
#  define NV30_TX_RECTANGLE                             (1 << 14)
#  define NV30_TX_FORMAT_SHIFT                          8
#  define NV30_TX_FORMAT_MASK                           (0x1F << 8) /* *bad* guess */
#    define NV30_TX_FORMAT_L8       0x01
#    define NV30_TX_FORMAT_A1R5G5B5 0x02
#    define NV30_TX_FORMAT_A4R4G4B4 0x03
#    define NV30_TX_FORMAT_R5G6B5   0x04
#    define NV30_TX_FORMAT_A8R8G8B8 0x05
#    define NV30_TX_FORMAT_DXT1     0x06
#    define NV30_TX_FORMAT_DXT3     0x07
#    define NV30_TX_FORMAT_DXT5     0x08
#    define NV30_TX_FORMAT_L16      0x14
#    define NV30_TX_FORMAT_G16R16   0x15    /* possibly wrong */
#    define NV30_TX_FORMAT_A8L8     0x18    /* possibly wrong */
#  define NV30_TX_NCOMP_SHIFT                           4            /* 2=2D, 3=3D*/
#  define NV30_TX_NCOMP_MASK                            (0x3 << 4)   /* possibly wrong */
#  define NV30_TX_CUBIC                                 (1 << 2)
#  define NV30_TX_WRAP_S_SHIFT                          0
#  define NV30_TX_WRAP_S_MASK                           (0xF << 0)
#  define NV30_TX_WRAP_T_SHIFT                          8
#  define NV30_TX_WRAP_T_MASK                           (0xF << 8)
#  define NV30_TX_WRAP_R_SHIFT                          16
#  define NV30_TX_WRAP_R_MASK                           (0xF << 16)
#    define NV30_TX_REPEAT           1
#    define NV30_TX_MIRRORED_REPEAT  2
#    define NV30_TX_CLAMP_TO_EDGE    3
#    define NV30_TX_CLAMP_TO_BORDER  4
#    define NV30_TX_CLAMP            5
/* DWORD 3 */
/* DWORD 4
    Appears to be related to swizzling of the texture image data into a RGBA value.
    A lot of uncertainty here...
*/
#  define NV30_TX_S0_X_SHIFT                            14
#  define NV30_TX_S0_Y_SHIFT                            12
#  define NV30_TX_S0_Z_SHIFT                            10
#  define NV30_TX_S0_W_SHIFT                            8
#    define NV30_TX_S0_ZERO 0
#    define NV30_TX_S0_ONE  1
#    define NV30_TX_S0_S1   2 /* take value from NV30_TX_S1_* */
#  define NV30_TX_S1_X_SHIFT                            6
#  define NV30_TX_S1_Y_SHIFT                            4
#  define NV30_TX_S1_Z_SHIFT                            2
#  define NV30_TX_S1_W_SHIFT                            0
#    define NV30_TX_S1_X    3
#    define NV30_TX_S1_Y    2
#    define NV30_TX_S1_Z    1
#    define NV30_TX_S1_W    0
/* DWORD 5 */
#  define NV30_TX_MIN_FILTER_SHIFT                      16
#  define NV30_TX_MIN_FILTER_MASK                       (0xF << 16)
#  define NV30_TX_MAG_FILTER_SHIFT                      24
#  define NV30_TX_MAG_FILTER_MASK                       (0xF << 24)
#    define NV30_TX_FILTER_NEAREST                1
#    define NV30_TX_FILTER_LINEAR                 2
#    define NV30_TX_FILTER_NEAREST_MIPMAP_NEAREST 3
#    define NV30_TX_FILTER_LINEAR_MIPMAP_NEAREST  4
#    define NV30_TX_FILTER_NEAREST_MIPMAP_LINEAR  5
#    define NV30_TX_FILTER_LINEAR_MIPMAP_LINEAR   6
/* DWORD 6 */
#  define NV30_TX_WIDTH_SHIFT                           16
#  define NV30_TX_WIDTH_MASK                            (0xFFFF << 16)
#  define NV30_TX_HEIGHT_SHIFT                          0
#  define NV30_TX_HEIGHT_MASK                           (0xFFFF << 0)
/* DWORD 7 */


#define NV30_TX_DEPTH                                   0x1840
#define NV30_TX_DEPTH_UNIT(n)                           (0x1840 + n*4)
#  define NV30_TX_DEPTH_SHIFT                           20
#  define NV30_TX_DEPTH_MASK                            (0xFFF << 20)
#  define NV30_TX_DEPTH_NPOT                            (1 << 7) /* also set for RECT, even if POT */

/* Vertex Program upload / control */
#define NV40_VP_UPLOAD_FROM_ID         0x1E9C /* The next VP_UPLOAD_INST is uploading instruction <n> (guess..) */
#define NV40_VP_PROGRAM_START_ID       0x1EA0 /* Start executing program from instruction <n> */



/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
#define NV40_VP_INST0_UNK0                (1 << 30) /* set when writing result regs */
#define NV40_VP_INST_COND_UPDATE_ENABLE   ((1 << 14)|1<<29) /* unsure about this */
#define NV40_VP_INST_INDEX_INPUT          (1 << 27) /* Use an address reg as in index into attribs */
#define NV40_VP_INST_COND_REG_SELECT_1    (1 << 25)
#define NV40_VP_INST_ADDR_REG_SELECT_1    (1 << 24)
#define NV40_VP_INST_SRC2_ABS             (1 << 23)
#define NV40_VP_INST_SRC1_ABS             (1 << 22)
#define NV40_VP_INST_SRC0_ABS             (1 << 21)
#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT  15
#define NV40_VP_INST_VEC_DEST_TEMP_MASK   (0x3F << 15)
#define NV40_VP_INST_COND_TEST_ENABLE     (1 << 13) /* write masking based on condition test */
#define NV40_VP_INST_COND_SHIFT           10
#define NV40_VP_INST_COND_MASK            (0x7 << 10)
#    define NV40_VP_INST_COND_FL     0
#    define NV40_VP_INST_COND_LT     1
#    define NV40_VP_INST_COND_EQ     2
#    define NV40_VP_INST_COND_LE     3
#    define NV40_VP_INST_COND_GT     4
#    define NV40_VP_INST_COND_NE     5
#    define NV40_VP_INST_COND_GE     6
#    define NV40_VP_INST_COND_TR     7
#define NV40_VP_INST_COND_SWZ_X_SHIFT     8
#define NV40_VP_INST_COND_SWZ_X_MASK      (3 << 8)
#define NV40_VP_INST_COND_SWZ_Y_SHIFT     6
#define NV40_VP_INST_COND_SWZ_Y_MASK      (3 << 6)
#define NV40_VP_INST_COND_SWZ_Z_SHIFT     4
#define NV40_VP_INST_COND_SWZ_Z_MASK      (3 << 4)
#define NV40_VP_INST_COND_SWZ_W_SHIFT     2
#define NV40_VP_INST_COND_SWZ_W_MASK      (3 << 2)
#define NV40_VP_INST_COND_SWZ_ALL_SHIFT   2
#define NV40_VP_INST_COND_SWZ_ALL_MASK    (0xFF << 2)
#define NV40_VP_INST_ADDR_SWZ_SHIFT       0
#define NV40_VP_INST_ADDR_SWZ_MASK        (0x03 << 0)
#define NV40_VP_INST0_KNOWN ( \
        NV40_VP_INST_INDEX_INPUT | \
        NV40_VP_INST_COND_REG_SELECT_1 | \
        NV40_VP_INST_ADDR_REG_SELECT_1 | \
        NV40_VP_INST_SRC2_ABS | \
        NV40_VP_INST_SRC1_ABS | \
        NV40_VP_INST_SRC0_ABS | \
        NV40_VP_INST_VEC_DEST_TEMP_MASK | \
        NV40_VP_INST_COND_TEST_ENABLE | \
        NV40_VP_INST_COND_MASK | \
        NV40_VP_INST_COND_SWZ_ALL_MASK | \
        NV40_VP_INST_ADDR_SWZ_MASK)

/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
#define NV40_VP_INST_VEC_OPCODE_SHIFT     22
#define NV40_VP_INST_VEC_OPCODE_MASK      (0x1F << 22)
#    define NV40_VP_INST_OP_NOP           0x00
#    define NV40_VP_INST_OP_MOV           0x01
#    define NV40_VP_INST_OP_MUL           0x02
#    define NV40_VP_INST_OP_ADD           0x03
#    define NV40_VP_INST_OP_MAD           0x04
#    define NV40_VP_INST_OP_DP3           0x05
#    define NV40_VP_INST_OP_DP4           0x07
#    define NV40_VP_INST_OP_DPH           0x06
#    define NV40_VP_INST_OP_DST           0x08
#    define NV40_VP_INST_OP_MIN           0x09
#    define NV40_VP_INST_OP_MAX           0x0A
#    define NV40_VP_INST_OP_SLT           0x0B
#    define NV40_VP_INST_OP_SGE           0x0C
#    define NV40_VP_INST_OP_ARL           0x0D
#    define NV40_VP_INST_OP_FRC           0x0E
#    define NV40_VP_INST_OP_FLR           0x0F
#    define NV40_VP_INST_OP_SEQ           0x10
#    define NV40_VP_INST_OP_SFL           0x11
#    define NV40_VP_INST_OP_SGT           0x12
#    define NV40_VP_INST_OP_SLE           0x13
#    define NV40_VP_INST_OP_SNE           0x14
#    define NV40_VP_INST_OP_STR           0x15
#    define NV40_VP_INST_OP_SSG           0x16
#    define NV40_VP_INST_OP_ARR           0x17
#    define NV40_VP_INST_OP_ARA           0x18
#define NV40_VP_INST_SCA_OPCODE_SHIFT     27
#define NV40_VP_INST_SCA_OPCODE_MASK      (0x1F << 27)
#    define NV40_VP_INST_OP_RCP           0x02
#    define NV40_VP_INST_OP_RCC           0x03
#    define NV40_VP_INST_OP_RSQ           0x04
#    define NV40_VP_INST_OP_EXP           0x05
#    define NV40_VP_INST_OP_LOG           0x06
#    define NV40_VP_INST_OP_LIT           0x07
#    define NV40_VP_INST_OP_BRA           0x09
#    define NV40_VP_INST_OP_CAL           0x0B
#    define NV40_VP_INST_OP_RET           0x0C
#    define NV40_VP_INST_OP_LG2           0x0D
#    define NV40_VP_INST_OP_EX2           0x0E
#    define NV40_VP_INST_OP_SIN           0x0F
#    define NV40_VP_INST_OP_COS           0x10
#    define NV40_VP_INST_OP_PUSHA         0x13
#    define NV40_VP_INST_OP_POPA          0x14
#define NV40_VP_INST_CONST_SRC_SHIFT      12
#define NV40_VP_INST_CONST_SRC_MASK       (0xFF << 12)
#define NV40_VP_INST_INPUT_SRC_SHIFT      8 
#define NV40_VP_INST_INPUT_SRC_MASK       (0x0F << 8)
#    define NV40_VP_INST_IN_POS           0      /* These seem to match the bindings specified in   */
#    define NV40_VP_INST_IN_WEIGHT        1      /* the ARB_v_p spec (2.14.3.1)                     */
#    define NV40_VP_INST_IN_NORMAL        2      
#    define NV40_VP_INST_IN_COL0          3      /* Should probably confirm them all thougth        */
#    define NV40_VP_INST_IN_COL1          4
#    define NV40_VP_INST_IN_FOGC          5
#    define NV40_VP_INST_IN_TC0           8
#    define NV40_VP_INST_IN_TC(n)         (8+n)
#define NV40_VP_INST_SRC0H_SHIFT          0
#define NV40_VP_INST_SRC0H_MASK           (0xFF << 0)
#define NV40_VP_INST1_KNOWN ( \
        NV40_VP_INST_VEC_OPCODE_MASK | \
        NV40_VP_INST_SCA_OPCODE_MASK | \
        NV40_VP_INST_CONST_SRC_MASK  | \
        NV40_VP_INST_INPUT_SRC_MASK  | \
        NV40_VP_INST_SRC0H_MASK \
        )

/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
#define NV40_VP_INST_SRC0L_SHIFT          23
#define NV40_VP_INST_SRC0L_MASK           (0x1FF << 23)
#define NV40_VP_INST_SRC1_SHIFT           6
#define NV40_VP_INST_SRC1_MASK            (0x1FFFF << 6)
#define NV40_VP_INST_SRC2H_SHIFT          0
#define NV40_VP_INST_SRC2H_MASK           (0x3F << 0)
#define NV40_VP_INST_IADDRH_SHIFT         0
#define NV40_VP_INST_IADDRH_MASK          (0x1F << 0) /* guess, need to test this */

/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
#define NV40_VP_INST_IADDRL_SHIFT         29        
#define NV40_VP_INST_IADDRL_MASK          (7 << 29)
#define NV40_VP_INST_SRC2L_SHIFT          21
#define NV40_VP_INST_SRC2L_MASK           (0x7FF << 21)
#define NV40_VP_INST_SCA_WRITEMASK_SHIFT      17
#define NV40_VP_INST_SCA_WRITEMASK_MASK       (0xF << 17)
#    define NV40_VP_INST_SCA_WRITEMASK_X      (1 << 20)
#    define NV40_VP_INST_SCA_WRITEMASK_Y      (1 << 19)
#    define NV40_VP_INST_SCA_WRITEMASK_Z      (1 << 18)
#    define NV40_VP_INST_SCA_WRITEMASK_W      (1 << 17)
#define NV40_VP_INST_VEC_WRITEMASK_SHIFT      13
#define NV40_VP_INST_VEC_WRITEMASK_MASK       (0xF << 13)
#    define NV40_VP_INST_VEC_WRITEMASK_X      (1 << 16)
#    define NV40_VP_INST_VEC_WRITEMASK_Y      (1 << 15)
#    define NV40_VP_INST_VEC_WRITEMASK_Z      (1 << 14)
#    define NV40_VP_INST_VEC_WRITEMASK_W      (1 << 13)
#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT   7
#define NV40_VP_INST_SCA_DEST_TEMP_MASK    (0x3F << 7)
#define NV40_VP_INST_DEST_SHIFT           2
#define NV40_VP_INST_DEST_MASK            (31 << 2)
#    define NV40_VP_INST_DEST_POS         0
#    define NV40_VP_INST_DEST_COL0        1
#    define NV40_VP_INST_DEST_COL1        2
#    define NV40_VP_INST_DEST_BFC0        3
#    define NV40_VP_INST_DEST_BFC1        4
#    define NV40_VP_INST_DEST_FOGC        5
#    define NV40_VP_INST_DEST_PSZ         6
#    define NV40_VP_INST_DEST_TC0         7
#    define NV40_VP_INST_DEST_TC(n)       (7+n)
#    define NV40_VP_INST_DEST_TEMP        0x1F     /* see NV40_VP_INST0_* for actual register */
#define NV40_VP_INST_INDEX_CONST          (1 << 1)
#define NV40_VP_INST_UNK_00               (1 << 0) /* appears to be set on the last inst only */
#define NV40_VP_INST3_KNOWN ( \
        NV40_VP_INST_SRC2L_MASK |\
        NV40_VP_INST_SCA_WRITEMASK_MASK |\
        NV40_VP_INST_VEC_WRITEMASK_MASK |\
        NV40_VP_INST_SCA_DEST_TEMP_MASK |\
        NV40_VP_INST_DEST_MASK |\
        NV40_VP_INST_INDEX_CONST)

/* Useful to split the source selection regs into their pieces */
#define NV40_VP_SRC0_HIGH_SHIFT 9
#define NV40_VP_SRC0_HIGH_MASK  0x0001FE00
#define NV40_VP_SRC0_LOW_MASK   0x000001FF
#define NV40_VP_SRC2_HIGH_SHIFT 11
#define NV40_VP_SRC2_HIGH_MASK  0x0001F800
#define NV40_VP_SRC2_LOW_MASK   0x000007FF

/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
#define NV40_VP_SRC_NEGATE               (1 << 16)
#define NV40_VP_SRC_SWZ_X_SHIFT          14
#define NV40_VP_SRC_SWZ_X_MASK           (3 << 14)
#define NV40_VP_SRC_SWZ_Y_SHIFT          12
#define NV40_VP_SRC_SWZ_Y_MASK           (3 << 12)
#define NV40_VP_SRC_SWZ_Z_SHIFT          10
#define NV40_VP_SRC_SWZ_Z_MASK           (3 << 10)
#define NV40_VP_SRC_SWZ_W_SHIFT          8
#define NV40_VP_SRC_SWZ_W_MASK           (3 << 8)
#define NV40_VP_SRC_SWZ_ALL_SHIFT        8
#define NV40_VP_SRC_SWZ_ALL_MASK         (0xFF << 8)
#define NV40_VP_SRC_TEMP_SRC_SHIFT       2
#define NV40_VP_SRC_TEMP_SRC_MASK        (0x3F << 2)
#define NV40_VP_SRC_REG_TYPE_SHIFT       0
#define NV40_VP_SRC_REG_TYPE_MASK        (3 << 0)
#    define NV40_VP_SRC_REG_TYPE_UNK0    0
#    define NV40_VP_SRC_REG_TYPE_TEMP    1
#    define NV40_VP_SRC_REG_TYPE_INPUT   2
#    define NV40_VP_SRC_REG_TYPE_CONST   3

//== Opcode / Destination selection ==
#define NV40_FP_OP_PROGRAM_END      (1 << 0)
#define NV40_FP_OP_OUT_REG_SHIFT    1
#define NV40_FP_OP_OUT_REG_MASK    (31 << 1)    /* uncertain */
#define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8)
#define NV40_FP_OP_OUTMASK_SHIFT    9
#define NV40_FP_OP_OUTMASK_MASK    (0xF << 9)
#    define NV40_FP_OP_OUT_X        (1 << 9)
#    define NV40_FP_OP_OUT_Y        (1 << 10)
#    define NV40_FP_OP_OUT_Z        (1 << 11)
#    define NV40_FP_OP_OUT_W        (1 << 12)
/* Uncertain about these, especially the input_src values.. it's possible that
 * they can be dynamically changed.
 */
#define NV40_FP_OP_INPUT_SRC_SHIFT    13
#define NV40_FP_OP_INPUT_SRC_MASK    (15 << 13)
#    define NV40_FP_OP_INPUT_SRC_POSITION    0x0
#    define NV40_FP_OP_INPUT_SRC_COL0        0x1
#    define NV40_FP_OP_INPUT_SRC_COL1        0x2
#    define NV40_FP_OP_INPUT_SRC_FOGC        0x3
#    define NV40_FP_OP_INPUT_SRC_TC0         0x4
#    define NV40_FP_OP_INPUT_SRC_TC(n)       (0x4 + n)
#define NV40_FP_OP_TEX_UNIT_SHIFT    17
#define NV40_FP_OP_TEX_UNIT_MASK    (0xF << 17) /* guess */
#define NV40_FP_OP_PRECISION_SHIFT 22
#define NV40_FP_OP_PRECISION_MASK  (3 << 22)
#   define NV40_FP_PRECISION_FP32  0
#   define NV40_FP_PRECISION_FP16  1
#   define NV40_FP_PRECISION_FX12  2
#define NV40_FP_OP_OPCODE_SHIFT    24
#define NV40_FP_OP_OPCODE_MASK        (0x3F << 24)
#    define NV40_FP_OP_OPCODE_NOP    0x00
#    define NV40_FP_OP_OPCODE_MOV    0x01
#    define NV40_FP_OP_OPCODE_MUL    0x02
#    define NV40_FP_OP_OPCODE_ADD    0x03
#    define NV40_FP_OP_OPCODE_MAD    0x04
#    define NV40_FP_OP_OPCODE_DP3    0x05
#    define NV40_FP_OP_OPCODE_DP4    0x06
#    define NV40_FP_OP_OPCODE_DST    0x07
#    define NV40_FP_OP_OPCODE_MIN    0x08
#    define NV40_FP_OP_OPCODE_MAX    0x09
#    define NV40_FP_OP_OPCODE_SLT    0x0A
#    define NV40_FP_OP_OPCODE_SGE    0x0B
#    define NV40_FP_OP_OPCODE_SLE    0x0C
#    define NV40_FP_OP_OPCODE_SGT    0x0D
#    define NV40_FP_OP_OPCODE_SNE    0x0E
#    define NV40_FP_OP_OPCODE_SEQ    0x0F
#    define NV40_FP_OP_OPCODE_FRC    0x10
#    define NV40_FP_OP_OPCODE_FLR    0x11
#    define NV40_FP_OP_OPCODE_PK4B   0x13
#    define NV40_FP_OP_OPCODE_UP4B   0x14
#    define NV40_FP_OP_OPCODE_DDX    0x15 /* can only write XY */
#    define NV40_FP_OP_OPCODE_DDY    0x16 /* can only write XY */
#    define NV40_FP_OP_OPCODE_TEX    0x17
#    define NV40_FP_OP_OPCODE_TXP    0x18
#    define NV40_FP_OP_OPCODE_TXD    0x19
#    define NV40_FP_OP_OPCODE_RCP    0x1A
#    define NV40_FP_OP_OPCODE_EX2    0x1C
#    define NV40_FP_OP_OPCODE_LG2    0x1D
#    define NV40_FP_OP_OPCODE_COS    0x22
#    define NV40_FP_OP_OPCODE_SIN    0x23
#    define NV40_FP_OP_OPCODE_PK2H   0x24
#    define NV40_FP_OP_OPCODE_UP2H   0x25
#    define NV40_FP_OP_OPCODE_PK4UB  0x27
#    define NV40_FP_OP_OPCODE_UP4UB  0x28
#    define NV40_FP_OP_OPCODE_PK2US  0x29
#    define NV40_FP_OP_OPCODE_UP2US  0x2A
#    define NV40_FP_OP_OPCODE_DP2A   0x2E
#    define NV40_FP_OP_OPCODE_TXL    0x2F
#    define NV40_FP_OP_OPCODE_TXB    0x31
#    define NV40_FP_OP_OPCODE_DIV    0x3A
/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
#    define NV40_FP_OP_BRA_OPCODE_BRK    0x0
#    define NV40_FP_OP_BRA_OPCODE_CAL    0x1
#    define NV40_FP_OP_BRA_OPCODE_IF     0x2
#    define NV40_FP_OP_BRA_OPCODE_LOOP   0x3
#    define NV40_FP_OP_BRA_OPCODE_REP    0x4
#    define NV40_FP_OP_BRA_OPCODE_RET    0x5
#define NV40_FP_OP_OUT_SAT            (1 << 31)

/* high order bits of SRC0 */
#define NV40_FP_OP_OUT_ABS            (1 << 29)
#define NV40_FP_OP_COND_SWZ_W_SHIFT   27
#define NV40_FP_OP_COND_SWZ_W_MASK    (3 << 27)
#define NV40_FP_OP_COND_SWZ_Z_SHIFT   25
#define NV40_FP_OP_COND_SWZ_Z_MASK    (3 << 25)
#define NV40_FP_OP_COND_SWZ_Y_SHIFT   23
#define NV40_FP_OP_COND_SWZ_Y_MASK    (3 << 23)
#define NV40_FP_OP_COND_SWZ_X_SHIFT   21
#define NV40_FP_OP_COND_SWZ_X_MASK    (3 << 21)
#define NV40_FP_OP_COND_SWZ_ALL_SHIFT 21
#define NV40_FP_OP_COND_SWZ_ALL_MASK  (0xFF << 21)
#define NV40_FP_OP_COND_SHIFT         18
#define NV40_FP_OP_COND_MASK          (0x07 << 18)
#    define NV40_FP_OP_COND_FL     0
#    define NV40_FP_OP_COND_LT     1
#    define NV40_FP_OP_COND_EQ     2
#    define NV40_FP_OP_COND_LE     3
#    define NV40_FP_OP_COND_GT     4
#    define NV40_FP_OP_COND_NE     5
#    define NV40_FP_OP_COND_GE     6
#    define NV40_FP_OP_COND_TR     7

/* high order bits of SRC1 */
#define NV40_FP_OP_SRC_SCALE_SHIFT    28
#define NV40_FP_OP_SRC_SCALE_MASK     (3 << 28)

/* SRC1 LOOP */
#define NV40_FP_OP_LOOP_INCR_SHIFT    19
#define NV40_FP_OP_LOOP_INCR_MASK     (0xFF << 19)
#define NV40_FP_OP_LOOP_INDEX_SHIFT   10
#define NV40_FP_OP_LOOP_INDEX_MASK    (0xFF << 10)
#define NV40_FP_OP_LOOP_COUNT_SHIFT   2
#define NV40_FP_OP_LOOP_COUNT_MASK    (0xFF << 2) /* from MAX_PROGRAM_LOOP_COUNT_NV */

/* SRC1 IF */
#define NV40_FP_OP_ELSE_ID_SHIFT      2
#define NV40_FP_OP_ELSE_ID_MASK       (0xFF << 2) /* UNKNOWN */

/* SRC1 CAL */
#define NV40_FP_OP_IADDR_SHIFT        2
#define NV40_FP_OP_IADDR_MASK         (0xFF << 2)

/* SRC1 REP
 *   I have no idea why there are 3 count values here..  but they
 *   have always been filled with the same value in my tests so
 *   far..
 */
#define NV40_FP_OP_REP_COUNT1_SHIFT   2
#define NV40_FP_OP_REP_COUNT1_MASK    (0xFF << 2)
#define NV40_FP_OP_REP_COUNT2_SHIFT   10
#define NV40_FP_OP_REP_COUNT2_MASK    (0xFF << 10)
#define NV40_FP_OP_REP_COUNT3_SHIFT   19
#define NV40_FP_OP_REP_COUNT3_MASK    (0xFF << 19)

/* SRC2 REP/IF */
#define NV40_FP_OP_END_ID_SHIFT       2
#define NV40_FP_OP_END_ID_MASK        (0xFF << 2) /* UNKNOWN */

// SRC2 high-order
#define NV40_FP_OP_INDEX_INPUT        (1 << 30)
#define NV40_FP_OP_ADDR_INDEX_SHIFT   19
#define NV40_FP_OP_ADDR_INDEX_MASK    (0xF << 19) //UNKNOWN

//== Register selection ==
#define NV40_FP_REG_SRC_INPUT        (1 << 0)    /* uncertain */
#define NV40_FP_REG_SRC_CONST        (1 << 1)
#define NV40_FP_REG_SRC_SHIFT        2            /* uncertain */
#define NV40_FP_REG_SRC_MASK        (31 << 2)
#define NV40_FP_REG_UNK_0            (1 << 8)
#define NV40_FP_REG_SWZ_ALL_SHIFT    9
#define NV40_FP_REG_SWZ_ALL_MASK    (255 << 9)
#define NV40_FP_REG_SWZ_X_SHIFT    9
#define NV40_FP_REG_SWZ_X_MASK        (3 << 9)
#define NV40_FP_REG_SWZ_Y_SHIFT    11
#define NV40_FP_REG_SWZ_Y_MASK        (3 << 11)
#define NV40_FP_REG_SWZ_Z_SHIFT    13
#define NV40_FP_REG_SWZ_Z_MASK        (3 << 13)
#define NV40_FP_REG_SWZ_W_SHIFT    15
#define NV40_FP_REG_SWZ_W_MASK        (3 << 15)
#    define NV40_FP_SWIZZLE_X        0
#    define NV40_FP_SWIZZLE_Y        1
#    define NV40_FP_SWIZZLE_Z        2
#    define NV40_FP_SWIZZLE_W        3
#define NV40_FP_REG_NEGATE            (1 << 17)

#endif

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