Vertex programs instruction set

128bit opcodes, split into 4 32-bit ones for ease of use.

Non-native instructions

ABS - MOV + NV40_VP_INST0_DEST_ABS
POW - EX2 + MUL + LG2
SUB - ADD, second source negated
SWZ - MOV
XPD -

Register access

• Only one INPUT can be accessed per-instruction (move extras into TEMPs)
• Only one CONST can be accessed per-instruction (move extras into TEMPs)

Relative Addressing

According to the value returned for MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB there are only two address registers available. The destination in the ARL instruction is set to TEMP <n> (The temp isn't actually written).

When using vanilla ARB_v_p, the proprietary driver will squish both the available ADDRESS regs into the first hardware reg in the X and Y components.

To use an address reg as an index into consts, the CONST_SRC is set to (const_base + offset) and INDEX_CONST is set.

It is similar for inputs, INPUT_SRC is set to the offset value and INDEX_INPUT is set.

To access the second address reg use ADDR_REG_SELECT_1. A particular component of the address regs is selected with ADDR_SWZ.

Only one address register can be accessed per instruction, but you may use the address reg as an index into both consts and inputs in the same instruction as long as the swizzles also match.

Conditional execution (see NV_vertex_program{2,3} for details)

All instructions appear to be able to modify one of two condition code registers. This is enabled by setting COND_UPDATE_ENABLE. The second condition registers is updated by setting COND_REG_SELECT_1.

Conditional execution of an instruction is enabled by setting COND_TEST_ENABLE, and selecting the condition which will allow the test to pass with COND_{FL,LT,...}. It is possible to swizzle the values in the condition register, which allows for testing against an individual component.

Branching

The BRA/CAL instructions seem to follow a slightly different opcode layout. The destination instruction ID (IADDR) overlaps SRC2. Instruction ID's seem to be numbered based on the UPLOAD_FROM_ID FIFO command, and is incremented automatically on each UPLOAD_INST FIFO command.

Conditional branching is achieved by using the condition tests described above. There doesn't appear to be dedicated looping instructions, but this can be done using a temp reg + conditional branching.

Subroutines may be uploaded before the main program itself, but the first executed instruction is determined by the PROGRAM_START_ID FIFO command.

Todo:

Texture lookup

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